True Circuits offers six general categories of low-jitter PLL hard macros: Ultra PLLs, IoT PLLs, General Purpose PLLs, Clock Generator PLLs, Spread Spectrum PLLs, and Deskew PLLs. We also offer low-jitter Multi-slave DDR DLL and Multi-phase DLL hard macros. These hard macros have excellent jitter performance while operating in the hostile mixed-signal noise environment present in today’s ICs. They span nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. Our PLLs support wide frequency and multiplication factor ranges, ultra low jitter and are fully pin programmable. Our DLLs have excellent linearity, very high resolution and are ideal for high-speed DDR and other interface applications. These PLL and DLL hard macros are available in TSMC, GLOBALFOUNDRIES and UMC logic processes from 180nm to 7nm.

True Circuits now offers a PLL specifically tailored to the stringent power requirements and wide frequency operation range of the rapidly-growing IoT market. Sipping only 45uW at 30MHz and running from core power, the IoT PLL is designed for very low power. With multiplication factors up to 8192, the PLL is able to run off of a small and inexpensive 32KHz crystal and still clock a 32-bit CPU at up to 250MHz. The IoT PLL is ideal for applications like wearables and senor devices, where the power-performance profile must be managed tightly, and possibly over a very wide frequency range.

True Circuits offers a state-of-the-art PLL that uses high-speed digital and analog circuits to achieve exceptional performance, with many useful features. The Ultra PLL is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<500fs) and ultra wide multiplication range (1-250,000). It offers precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. The PLL can also generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements.

True Circuits also offers a DDR 4/3 PHY that is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read data eye and gate timing are also continuously adjusted. Automatic training is included for multi-cycle read gate timing and write leveling, write data eye timing, and internal and external (on DRAM) Vref setting. Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, and is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is also DFI 3.1 compliant, and when combined with a suitable DDR 4/3 memory controller, a complete and fully-automatic DDR 4/3 system is realized. For more information see the DDR 4/3 PHY product page.

True Circuits’ continuous product improvements and product additions are driven by lab experience, customer requirements and our unique understanding of real world timing applications. Our Ultra PLL offers unprecedented performance, features and ease of use, opening new possibilities for our customers’ products. Our DDR 4/3 PHY is a fitting example of how we applied everything we know about DDR, timing circuits, parallel interfaces and signal integrity to develop a revolutionary product that will change the way our customers think about DDR.