Ultra PLL  (Frac-N)

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<500fs) for the most demanding SerDes and ADC reference clocks. It has ultra wide frequency range with multiplication factors over 250,000 to support reference clocks from 32KHz to 1GHz. It has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. It draws low power in a compact size.

IoT PLL

The IoT PLL is designed for very low power, sipping only about 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to run off of a small and inexpensive 32KHz crystal and still clock a 32-bit CPU at up to around 250MHz. It is ideal for IoT applications like wearables and senor devices, where the power-performance profile must be managed tightly, and possibly over a very wide frequency range.

General Purpose PLL

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.

Clock Generator PLL

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. It supports fractional-N multiplication with additional external low speed logic. The outputs are 50% duty cycle for all output divider values.

Spread Spectrum PLL  (Frac-N)

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications that require low EMI. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-256 or larger integer divider and a 1-256 or larger fractional divider in the internal feedback path, with as many as 4 bits of precise fractional-N control, and a 1-8 divider at the output. It can generate precise and adjustable frequency spreading depths (1.5% typical and up to around 10%) and rates (30KHz typical). The outputs are 50% duty cycle for all output divider values.

Deskew PLL

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.