News
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3 Nov 17
True Circuits Attends the TSMC 2017 China OIP Ecosystem Forum
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7 Sep 17
True Circuits Attends the TSMC 2017 NA OIP Ecosystem Forum
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7 Nov 17
True Circuits Signs Five Year PLL License with Tsinghua University in China
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14 Jun 17
True Circuits Attends Design Automation Conference
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14 Mar 17
True Circuits Showcases State-of-the-art Ultra PLL, Low Power IoT PLL and 16nm IP Portfolio at TSMC NA Technology Symposiums
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30 May 16
True Circuits Attends Design Automation Conference
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14 Mar 16
True Circuits Announces New Line of IoT PLLs
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5 Jun 15
True Circuits Attends Design Automation Conference
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Ultra PLL
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<500fs) for the most demanding SerDes and ADC reference clocks. It has ultra wide frequency range with multiplication factors over 250,000 to support reference clocks from 32KHz to 1GHz. It has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. It draws low power in a compact size.