True Circuits Attends the TSMC 2017 China OIP Ecosystem Forum
January 6th, 2018November 3, 2017
True Circuits Attends the TSMC 2017 China OIP Ecosystem Forum
Showcases State-of-the-art Ultra PLL and Low Power IoT PLL in Shenzhen, China
Who
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries and member of the TSMC IP Alliance since 2004. TCI PLL and DLL IP has been used in more than 75 products by over 35 Chinese technology companies since 2007. TCI regards China as a key market for its IP designs and continues to expand market share and product reach with the help of its China sales representative, Pinnacle Design Systems, Ltd.
What
True Circuits will showcase its IoT PLLs that are specifically tailored to the stringent power requirements and wide frequency operation range of the rapidly-growing IoT market. Sipping only 45uW at 30MHz and running from core power, the IoT PLL is designed for very low power. With multiplication factors up to 8192, the PLL is able to run off of a small and inexpensive 32KHz crystal and still clock a 32-bit CPU at up to 250MHz. The IoT PLL is ideal for applications like wearables and senor devices, where the power-performance profile must be managed tightly, and possibly over a very wide frequency range.
True Circuits will also showcase its high-performance Ultra PLLs that are well suited for the most demanding chip applications, including high-speed SerDes and ADC input clocks. The Ultra PLL employs a state-of-the-art architecture and uses high-speed digital and analog circuits to achieve exceptional performance, with many useful features. It has ultra- low jitter (<500fs) for the most demanding SerDes and ADC input clocks. It has ultra-wide frequency range with multiplication factors from 3 to over 250,000, supporting reference clocks as low as 32KHz. It also has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can even generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. The Ultra PLL packs all these features into a compact size that draws low power and, with full pin programmability, one PLL can be used for all applications on a SoC.
True Circuits will also feature its complete line of standardized and silicon-proven general purpose, clock generator, deskew, and spread spectrum PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points, features and foundry processes typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant, reusable and available for delivery in TSMC processes from 180nm to 7nm, including most half nodes.
Brian Gardner, True Circuits’ V.P. of Business Development, will have an OIP presentation titled “Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems” published in the conference program. In wide chip interfaces like DDR, HBM and ONFI, it can be challenging to synthesize and connect high-frequency controllers to the PHY hard macros. Clock trees can be expansive, pushing tools to their limits, and often multiple clock domains are needed. Jitter can also be an issue on long paths. Brian’s presentation will show how True Circuits PLL and DLL IP is being used by multiple customers to build ONFI and HBM subsystems in advanced TSMC process nodes, and discuss the tradeoffs and timing budget concerns among different timing architectures. In addition, the presentation will explain how source-synchronous signaling is used in our DDR PHY to ease timing closure, and to allow the memory controller to be synthesized for high-frequency operation, which reduces its size and lowers its latency. By using a soft IP “shim” between the memory controller and PHY, the memory controller only needs a single localized clock tree, reducing mismatch and jitter. The long routes between the soft shim and the PHY hard macros are source-synchronous, so data/strobe groups need only be roughly matched, something easily accomplished by place and route tools.
When and Where
TSMC 2017 China OIP Ecosystem Forum
November 7, 2017: Intercontinental Hotel Shenzhen
Overseas Chinese Town, Nan Shan District, Shenzhen, 518053, China
About True Circuits PLLs and DLLs
In addition to the IoT and Ultra PLLs, True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, and spread spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors and functions over which they deliver optimal performance, avoiding the cost and complexity of licensing multiple point-solution PLLs from foundries or other vendors. TCI’s DLLs are available in mutli-slave and multi-phase versions and different sizes and form factors. They delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC processes from 180nm to 7nm. For more information about True Circuits IP products, visit www.truecircuits.com/tci_technology.html and www.truecircuits.com/product_matrix.html.
About True Circuits DDR PHYs
The DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read data eye and gate timing are also continuously adjusted. Automatic training is included for multi-cycle read gate timing and write leveling, write data eye timing, and internal and external (on DRAM) Vref setting.
The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, and is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is also DFI 3.1 compliant, and when combined with a suitable DDR 4/3 memory controller, a complete and fully-automatic DDR 4/3 system is realized.
The True Circuits DDR 4/3 PHY is initially available for customer delivery in TSMC’s 28nm HPC/HPC+ process. The PHY will be available in additional TSMC processes in the very near future. Interested customers can obtain more product information on the web at www.truecircuits.com/ddr_phy.html or by contacting True Circuits at sales@truecircuits.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI’s robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world’s leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 19 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers’ products with production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos, California 94022 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at sales@truecircuits.com.
U.S. Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404, kim@truecircuits.com.
China Press Contact: Lily Liu, Pinnacle Design Systems, Ltd., +86 137 7445 4807, lily@pinnacle-ipcores.com.