A: A CG PLL is the primary choice for generating a stable high-frequency clock, which is phase-locked to a lower-frequency reference clock. A CG PLL would typically be used to produce a processor clock, where the processor has no dependencies on the reference clock domain. TCI provides silicon-proven CG PLLs with low jitter, low power, and very large multiplication ranges.

A: A DS PLL, like a clock generator PLL, can produce an output clock which is phase-locked to the reference clock. However, unlike with clock generator PLLs, the feedback clock of the deskew PLL comes from somewhere along the clock distribution network of the chip (in clock generator PLLs, the feedback clock is internally provided within the PLL). DS PLLs are typically used to produce clocks to support off-chip IO interfaces. TCI provides silicon-proven DS PLLs with low jitter, low power, and low static phase offsets.

A: Compared to CG PLLs, DS PLLs need to run at higher bandwidths to control input-to-output jitter. This bandwidth constraint limits the amount of frequency multiplication that can be done. Also, achieving low static phase offset imposes other constraints that narrow the multiplication range. CG PLLs can use lower bandwidths and allow wider multiplication ranges.

A: Yes, with DS PLLs, there is a hard limit imposed on the delay associated with the feedback clock. Please refer in the IP’s “User Guidelines” documentation for more information.

A: For efficient use of frequency bandwidth, FCC guidelines dictate that consumer products (such as PCs and cell phones) limit their electromagnetic emission to an FCC-defined power spectrum mask. Since a major source of electromagnetic emission is a system’s clock, it is often necessary to “spread” these clock signals over a frequency band. The process of spreading is equivalent to wide-band frequency modulation. In doing so, the peak emitted clock power at a given frequency is reduced because clock power is no longer concentrated at a single frequency. TCI provides silicon-proven, low jitter, low power, and very large multiplication range SS PLLs that provide fine controllability of bandwidth, modulation depth and spreading rate.

A: TCI’s SS PLLs provide a triangular frequency profile between frequencies Fmax and Fmin. When the spreading is turned off, the PLL’s output frequency will settle to Fmax or to (Fmax+Fmin)/2, depending on the specific design. Please refer in the IP’s “User Guidelines” documentation for more information.

A: A GP PLL is a simplified version of the clock generator (CG) PLL. Compared to CG PLLs, GP PLLs use smaller area and consume less power. In return, these PLLs support a narrower frequency multiplication range and have slightly larger output jitter specifications. TCI provides silicon-proven GP PLLs that can be used in a wide variety of chip applications, particularly area, power and cost sensitive ones.

A: The high programmability of the PLLs makes it easier to conduct power/jitter trade-offs. Please see the discussion below for more details on these trade-offs.

A: If the reference clock is a highly-stable, low-jitter signal, for a given VCO frequency, one would do the following to minimize long-term and short-term jitter: • Set output divider (OD) as large as possible. • Set feedback divider (NF) as small as possible given OD. • Select reference divider (NR) based on OD and NF.

A: If the reference clock has large period jitter, its contribution can dominate the PLL’s overall period jitter performance. To minimize the period jitter for a given VCO frequency, one would do the following: • Set OD as large as possible. • Set NR as large as possible. • Set NF based on OD and NR.Note that to minimize all types of jitter, use large OD. This fact is a re-statement of a well known observation: To minimize jitter, run the VCO at as high a frequency as possible and then divide its output to get the desired output frequency.

A: DLL implementations can use analog or digital techniques. Analog DLLs typically have much better jitter performance than digital DLLs. Analog DLLs can continuously and smoothly track out delay variations caused by on-chip PVT (process, voltage, and temperature) fluctuations. Hence analog DLLs do not suffer from glitches, which frequently are observed in digital DLLs. Like digital DLLs, analog DLLs can also be placed on the same supply as the interface.TCI provides silicon-proven, low jitter, low power, and highly programmable (i.e. high resolution) DLLs that operate over a wide frequency range.

A: TCI DLLs employ analog techniques and are designed to provide a fixed delay equal to a programmable fraction of the reference clock. This approach makes the delay insensitive to PVT variations.

A: The high programmability of the DLLs allows for very high delay resolution. This delay resolution can allow you to adjust delays at tapeout, in ROM coding, or at boot time using a training algorithm, in order to dial in data eyes and compensate for non-ideal timing on chip, in the package, and on the board

A: The DDR interface is a source-synchronous interface that uses a single bus to carry data both to and from DRAMs. The clock is sent along with the data in the form of a data strobe signal (DQS) with a frequency equal to half of the data bit rate. For older DDR1/DDR2 interfaces, a TCI deskew PLL, which provides phase-aligned divide by 1, 2, and 4 clock outputs, can facilitate generating the system clock signals, data strobes, and internal double frequency clocks used to clock the output data. For DDR2 and higher standards, a TCI DLL can be used to center data strobe signals on the outgoing or incoming data valid windows and a TCI clock generator PLL can be used to generate the system clock. A TCI spread spectrum PLL can be used instead to generate the system clock to lower electro-magnetic interference (EMI).TCI has developed a line of DLLs and spread spectrum PLLs for DDR and non-DDR applications. TCI’s DLLs are designed to generate precise strobe signal delays that can be programmed from 0 to 360 degrees of the reference period. They delay multiple periodic or aperiodic signals independent of voltage and temperature and deliver optimal jitter performance over a wide frequency range. TCI’s spread-spectrum PLLs are designed to multiply an input clock by an integer or fixed-point number with a frequency spreading capability suitable for PC, networking and consumer electronics applications that require spread-spectrum clock sources to satisfy FCC requirements on electro-magnetic emissions.

A: TCI products are named using the following format:TCI-“process type”-“product type”, where: • TCI: Designates IP as a TCI product. • “process type”: Designates process node at which the IP is offered, and • “product type”: is the actual IP type, such as clock generator PLL, deskew PLL, DDR DLL, etc.Examples: • TCI-TN28HP-CGMPLL: Mid output-frequency-range (M) clock generator PLL in TSMC 28nm HP process node. • TCI-TN40G-DDRHDLL: High output-frequency-range (H) DDR DLL in TSMC 40G process node.

A: Although all TCI IPs have wide frequency ranges, we normally tailor each of our products to a specific operating frequency range to ensure optimum performance. The letters L, M, and H refer to low frequency, mid frequency, and high frequency ranges, respectively.

A: One of the difficulties in working with PLLs/DLLs is the sensitivity of their frequency response (bandwidth and damping factor) to supply voltage, temperature, and process conditions. This sensitivity forces the system designer to allocate extra margin which leads to a suboptimal system design. TCI’s self-biased PLL/DLL designs minimize these variations in frequency response by using analog design techniques, which makes it possible for the design to operate close to its optimal operating point regardless of environmental and process conditions

A: We provide all of the following for each of our PLLs: • Complete specifications • User guidelines (including functional, integration, layout, testability, packaging, and board-level guidelines) • Behavioral simulation model (Verilog) • Timing synthesis model (Synopsys .LIB) • Layout abstract (LEF) • Complete layout (GDSII) • Layout vs. schematic (LVS) netlist (SPICE)

A: No, for several reasons. • PLL simulations are very tricky to run. It is fairly straightforward to get results that show the PLL works either much better or much worse than it will in a real application. Part of the value that we offer is that we have the expertise to properly simulate these PLLs, and that we have done a thorough job at it. • In order to establish adequate performance margin to ensure correct operation under all circumstances, many thousands of simulations must be run under carefully established operating conditions, which requires keen insight into what can go wrong and how to excite possible failures. • We do not want customers relying on the simulated performance of our PLLs outside the specified operating ranges or instead of the specified performance numbers. The specified performance is carefully margined based, not only on our carefully obtained simulation results, but also on our insight into PLL designs. • There is no need to use the SPICE netlist to include in a circuit simulation of your complete design. Because the PLL is ideally acting as a stable clock source, any “system-level” simulations should use a “PULSE” statement instead. Margining for the impact of PLL jitter on setup time should be accomplished by reducing the effective clock period by the specified jitter levels, along with those from the clock tree. • It is not in our business interest to release the proprietary aspects of our PLL designs. Our design kits do not include any internal schematics and our license agreement does not permit reverse engineering of our PLL designs.

A: The Verilog model is very close but not perfect. • In steady state, the Verilog model does not model any jitter that might be present in the real PLL. • During startup, the Verilog model will achieve lock much more quickly than the actual PLL to speed up Verilog simulations. The PLL specifications list the correct time required to achieve lock. • The number of cycles required by the Verilog model for relock, after a clock source or runtime divider changes, is also less than the actual PLL. • After the PLL reset has been de-asserted, the PLL will proceed towards a “locked” state. During this transition from a low reset frequency to a higher operating frequency, the PLL outputs a few cycles that are higher in frequency then the final target frequency. The PLL specifications list the maximum overshoot level. The Verilog model may exhibit somewhat different behavior during this “locking” transient.In general, the chip operation should not depend on the behavior of the PLL output clock until the PLL is completely locked.

A: Not usually. All TCI cell names are prefixed by “TCI_cellname_”. As a result, TCI IPs do not conflict with each other, and they usually don’t conflict with customers’ cell names.

A: If you are using the LVS deck supplied by the foundry, you should not find any mismatches between the TCI supplied layout and LVS netlist. If you use your own non-standard LVS deck, then you might have matching problems. If you have LVS problems, please contact TCI Support at (650) 949-3400 or support@truecircuits.com.

A: The jitter specifications are established based on the worst-case performance of the PLLs under worst-case operating conditions (i.e. worst-case operating frequency, process condition, supply voltage, and temperature, and 10% VDD low-frequency supply/substrate noise) with appropriate margin for their intended applications. They are not indicative of the actual measured performance of the PLL which is typically much better. However, in our experience, budgeting for better performance from any PLL in most ASIC applications is a mistake.Period jitter is the time variation in the duration of clock periods. Its specification is given as +/-x% peak-to-peak, which means that under the worst-case operating conditions with a worst case of 10% VDD low-frequency supply/substrate noise, the clock period may occasionally become as much as x% shorter or x% longer than the nominal value. This +/-x% variation in cycle time must be included in timing budgets.The period jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the period jitter for any divided clock expressed in units of time cannot exceed the long-term jitter defined below.Input-to-output jitter, or tracking jitter, is the time deviation between the PLL output edges and the reference clock edges. This jitter is only significant at a clock-domain boundary, where data is sampled by or transmitted to a clock domain separate from that produced by the PLL.Long-term jitter is the time deviation between the PLL output edges and those of an ideal clock source. If the reference signal is perfectly periodic such that it has no jitter, long-term jitter and tracking jitter for the output signal are equivalent.

A: No, “period jitter plus long-term jitter” is not a useful quantity. Neither is “period jitter plus input-to-output jitter.” In the best-case scenario, long-term jitter is made of the same components as period jitter. That is why the long-term jitter number fundamentally must be greater than the period jitter number.

A: The PLL specifications, along with those from the clock distribution network and the clocked elements, play a key part in chip timing budgets. When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, period jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.Period jitter is significant for setup-time or cycle based path budgets, but not for hold-time or race path budgets. Clock distribution jitter is significant for setup-time budgets, but less so for hold-time budgets, depending on the clock distribution structure. Clock distribution skew is important for both setup-time and hold-time budgets. Static phase offset along with tracking jitter is significant for the setup and hold-time budgets of latches or registers receiving data at the chip interface. Finally, duty cycle error must be considered for latch-based designs where the timing of both clock edges is significant.An on-chip setup-time budget, which subtracts from the nominal clock period to form the worst-case clock period, would typically be composed of the following worst-case components: • 1/2 peak-to-peak PLL period jitter • 1/2 peak-to-peak jitter through clock distribution network • skew from clock distribution network • skew between different PLL outputs (only if multiple used) • PLL duty cycle error (only for latch-based designs which use both clock edges)An on-chip hold-time budget would typically be composed of the following worst-case components: • 1/2 peak-to-peak jitter between clock distribution network end points • skew from clock distribution network • appropriate margin for flip-flop hold-time characteristicsAn off-chip setup-time budget, which is used to form the worst-case clock period at the chip interface, would typically be composed of the following worst-case components: • 1/2 peak-to-peak PLL input-to-output jitter • PLL static phase offset • 1/2 peak-to-peak jitter through on-chip and off-chip clock distribution network • skew from on-chip and off-chip clock distribution network • PLL duty cycle error (only for latch-based designs which use both clock edges)An off-chip hold-time budget, would typically be composed of the following worst-case components: • 1/2 peak-to-peak PLL input-to-output jitter • PLL static phase offset • 1/2 peak-to-peak jitter through on-chip and off-chip clock distribution network • skew from on-chip and off-chip clock distribution network • PLL duty cycle error (only for latch-based designs which use both clock edges) • appropriate margin for flip-flop hold-time characteristicsThe peak-to-peak amount of jitter through a well designed clock distribution network will be approximately the clock distribution delay times the peak-to-peak expected supply noise in percent (assuming that a 1% change in supply voltage leads to a 0.5% change in delay).

A: Yes. Each PLL IP should have separate analog supply pads on the chip. The IP should be located near the edge of the chip, away from wide output buses. IP control pins should be made programmable via registers for maximum flexibility. Also the register interface should not rely on PLL outputs for proper operation. Please refer in the “User Guidelines” document that accompanies the IP for additional information.

A: No, the PLL/DLL does not include ESD protection. TCI expects the customer to apply standard ESD protection schemes at the chip level for all I/O pins (including power pins) of the IP. We believe this policy provides more flexibility to our customers which is valuable when trying to optimize their system.

A: Yes, PLLs can be placed in the I/O pad ring area. Please refer in the “User Guidelines” document that accompany the IP for more information.

A: Yes, you can cascade two PLLs. However, to minimize jitter amplification, the closed-loop bandwidth of the two PLLs should be separated by 2X or more. Typically, the upstream PLL will have the higher bandwidth and the downstream PLL will have the lower bandwidth.