The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance over a wide frequency range. The analog delay-line architecture used in our DLL design is internally isolated from supply noise for very low output jitter. The analog delay line also provides duty cycle correction.

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay line which rejects temperature and supply voltage variations, and has high supply noise rejection for very low jitter operation. TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution. TCI can also configure this block to output multi-phase clocks directly from the reference clock.
The analog delay-line architecture used in our DLL design sharply contrasts with those used in digital DLL approaches. The analog control loop allows our DLL to continuously and smoothly compensate its delays to changing voltage and temperature conditions, without any quantization jitter or output glitches. However, digital delay-line control loops, which typically multiplex between inverter outputs along a string of inverters, must select between quantized delay values. Such approaches can lead to imprecise delays and either output glitches from updates or timing drifts from voltage and temperature variations in the absence of updates. The analog delay line used in our DLL design is internally isolated from supply noise for very low output jitter, while digital delay lines tend to be very supply noise sensitive as they convert it percent-for-percent into output jitter. Our analog delay line also provides pulse width compensation to minimize pulse width distortion, unlike digital delay lines. Finally, our DLL design provides very high digital adjustment resolution (typically 7 bits), where the steps are precise fractions of the clock period, unlike digital DLL designs where the adjustment steps are very large and not well calibrated.

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. It supports fractional-N multiplication with additional external low speed logic. The outputs are 50% duty cycle for all output divider values.

The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<500fs) for the most demanding SerDes and ADC reference clocks. It has ultra wide frequency range with multiplication factors over 250,000 to support reference clocks from 32KHz to 1GHz. It has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. It draws low power in a compact size.

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications that require low EMI. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-256 or larger integer divider and a 1-256 or larger fractional divider in the internal feedback path, with as many as 4 bits of precise fractional-N control, and a 1-8 divider at the output. It can generate precise and adjustable frequency spreading depths (1.5% typical and up to around 10%) and rates (30KHz typical). The outputs are 50% duty cycle for all output divider values.