How PLLs differ?

Phase-Locked Loops have been in use on chips for almost 30 years. The basic interface is very straightforward, and so most PLLs offered as IP fit a standard model. They accept a reference clock and generate another clock, frequency multiplied and/or phase-locked to the reference. The differences between PLLs supplied by different vendors essentially come down to three things: the quality of the clocks produced, the useful feature sets of the individual PLLs, and the differences between the vendors themselves.

Clock Quality

The quality of a generated clock is measured by how much you have to degrade your timing budgets to account for imperfections in the PLL. The PLL’s maximum output jitter directly subtracts from the time available to your combinational logic to make your speed paths. A lower output jitter figure can get you that much closer to making your timing goals. TCI PLLs are designed from the outset with the goal of low jitter in a noisy mixed-signal environment.

Moreover, the performance of the PLL that you buy directly impacts the AC timing specifications that you promise your customers. Both output jitter and skew can subtract from the timing margin between your chip and the rest of the system. A poor PLL can make it difficult for a customer to use your chip, which can increase their time to market, reduce their packaging flexibility, or lead to poor reliability in service. In the worst case a poor PLL can convert a design win into a loss. The exceptional performance offered by TCI PLLs makes it easy for your customers to use your chip and can enhance your reputation as a supplier.

Feature Sets

The right PLL can make the design of the clocking system easier and more robust by providing flexible clock multiplication capability and multiple phase-locked outputs at different frequencies or at different precise fractional phase offsets of the clock period. TCI PLLs provide these features to minimize system integration effort.

The wrong PLL can impede chip bring-up and production ramp by requiring lab work to discover process-dependent tweaking factors necessary to make the PLL operate as specified. TCI PLLs are designed to operate optimally under all process and environmental conditions with no adjustments.

Vendor Differences

One crucial aspect of delivering your chip to your customers is characterizing it properly to help them design their systems. True Circuits will teach your engineers how to characterize the clocking system of your chip, both during design and after you receive prototype and production silicon. Proper characterization can help your customers through their design cycle. Having a reliable characterization of your chip can help you resolve interoperability issues that come up during your customer’s system bring-up.

PLLs don’t use much of your silicon real estate and shouldn’t use much of your engineering budget. True Circuit’s mission is to speed you through every aspect of your product cycle that involves your PLLs. That mission starts right now, before your purchase. You should find our website and phone support an excellent way to quickly get the information you need to close on your clocking system and move on to other issues.