News
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3 Nov 17
True Circuits Attends the TSMC 2017 China OIP Ecosystem Forum
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7 Sep 17
True Circuits Attends the TSMC 2017 NA OIP Ecosystem Forum
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7 Nov 17
True Circuits Signs Five Year PLL License with Tsinghua University in China
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14 Jun 17
True Circuits Attends Design Automation Conference
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14 Mar 17
True Circuits Showcases State-of-the-art Ultra PLL, Low Power IoT PLL and 16nm IP Portfolio at TSMC NA Technology Symposiums
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30 May 16
True Circuits Attends Design Automation Conference
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14 Mar 16
True Circuits Announces New Line of IoT PLLs
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5 Jun 15
True Circuits Attends Design Automation Conference
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Deskew PLL
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.