News
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3 Nov 17
True Circuits Attends the TSMC 2017 China OIP Ecosystem Forum
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7 Sep 17
True Circuits Attends the TSMC 2017 NA OIP Ecosystem Forum
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7 Nov 17
True Circuits Signs Five Year PLL License with Tsinghua University in China
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14 Jun 17
True Circuits Attends Design Automation Conference
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14 Mar 17
True Circuits Showcases State-of-the-art Ultra PLL, Low Power IoT PLL and 16nm IP Portfolio at TSMC NA Technology Symposiums
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30 May 16
True Circuits Attends Design Automation Conference
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14 Mar 16
True Circuits Announces New Line of IoT PLLs
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5 Jun 15
True Circuits Attends Design Automation Conference
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General Purpose PLL
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.